Design Verification Engineer – Gls & Hardware Emulation
Role Description & Overview
Hireroo Ltd in Barcelona seeks a Design Verification Engineer to drive gate-level simulation, hardware emulation and timing verification for advanced ASIC/SoC designs. You will collaborate with RTL, DFT, physical design and firmware teams to validate synthesized designs before silicon.
Mid to senior level, you will optimize simulation performance, automate workflows, debug RTL/netlist mismatches, and support emulation bring-up on hardware platforms while contributing to power, timing and
#J-18808-LjbffrReady to apply for this finance role?
This position is hosted on CV-Library. Click below to view the official posting and submit your application.
Key Details
- Date Posted: 27 Oct 2026
- Location: eixample
- Employment: Permanent
- Workplace: Hybrid
- Specialism: Engineering
Need an updated CV for this role?
Build an ATS-optimised finance CV in minutes with professional templates.
Build Free CV NowEmployer Profile
Hireroo Ltd
Verified Practice / CorporateVerified accountancy practice or enterprise finance team operating across the UK economy.
More Jobs at Hireroo Ltd